Semiconductor silicon carbide (SiC) has considerable bandgap energy in comparison with silicon that is widely used in devices, and is suitable for high voltage, high power, and high temperature operation. There are high expectations for its application to power devices and other components. The structure of SiC power devices, for which research and development are being actively carried out, can mainly be divided into two classes: MOS devices and junction devices. The present invention relates to a performance improvement in static induction transistors (SIT), junction field effect transistors (JFET), and other junction transistors.
Following are reported examples of SITs and JFETs in which SiC has been used.
Examples of a typical SIT have been disclosed in 600 V5A 4H-SiC SIT with Low RonS of 13 m Ω cm2 (Takashi Shinohe, and others, Proceedings of the Symposium on Static Induction Devices, Vol. 17, pp. 41-45) and 2002 Report on the Results of Research Sponsored by New Energy and Industrial Technology Development Organization, Development of Ultra Low Loss Power Devices Technology, and Device Design Technology (Research and Development Association for Future Electron Devices). FIG. 8 shows a cross-sectional schematic diagram of the SIT disclosed in 600 V5A 4H-SiC SIT with Low RonS of 13 m Ω cm2 by Takashi Shinohe, and others (Proceedings of the Symposium on Static Induction Devices, Vol. 17, pp. 41-45). The SIT 100 has a drain region 101 (an n-type low-resistance layer), a drift region 102 (an n-type high-resistance layer), source regions 103 of an n-type low-resistance region, gate regions 104 of a p-type low-resistance region formed so as to surround the source regions, a drain electrode 105, source electrodes 106, and gate electrodes 107. Channel regions 108 are formed between the gate regions 104. The SIT 100 does not have a channel-doped layer inside the drift region 102, but has a static induction transistor that exhibits a normally-on characteristic, which is in a conducting state when voltage is not applied to the gate electrodes 107. With this static induction transistor, high energy (MeV) ions are implanted when the gate region 104 is fabricated.
An example of a JFET is disclosed in 6A, 1 kV 4H-SiC Normally-off Trenched-and-Implanted Vertical JFETs (J. H. Zhao, et al., Materials Science Forum Vols. 457-460 (2004), pp. 1213-1216). FIG. 9 shows a cross-sectional structural diagram of a JFET disclosed in the preceding reference. The JFET 110 has a drain region 111 (an n-type low-resistance layer), a drift region 112 (an n-type high-resistance layer), source regions 113 of an n-type low-resistance layer, a p-type low-resistance region, p-type low-resistance gate regions 114, passivation films 115, a drain electrode 116, source electrodes 117, gate electrodes 118, trench portions 119, and a source metal layer 120. The width d of the source of the JFET is very narrow in a range of 1.45 μm to 1.95 μm. The depth D of the channel region is considerable at 2.1 μm. Additionally, with this JFET, in order to set the normally-off characteristic (non-conductive state) when voltage is not applied to the gate electrode 118, the width of the source must be made less than 1.95 μm, and such a width is very difficult to produce. In order to reduce the resistance of the gate region 114, a material with a high concentration of impurities is selected. Also, with this JFET, the gate region 114 is formed by several cycles of ion implantation in the bottom and side surfaces that have been deeply trench etched to 2 μm or greater.
FIGS. 10A, 10B, and 10C are diagrams that describe the operation of a static induction transistor (SIT), which is a typical junction transistor. In FIGS. 10A, 10B, and 10C, reference numeral 200 is a drain electrode, 201 is a drain region, 202 is a drift region, 203 is a source region, 204 is a gate region, 205 is a source electrode, 206 is a gate electrode, and 207 is a channel-doped layer. In this junction transistor, a voltage is applied to the drain electrode 200 and the source electrode 205 disposed on both surfaces of the substrate, and the main electric current that flows between the source and drain is controlled by signals applied to the gate electrode 206 that is disposed so as to surround the source region 203. Shown in this static induction transistor is an example of a normally-off type in which a channel-doped layer 207 is disposed so as to be connected to the gate region 204 in a high-resistance layer.
in this SIT, main electric current does not flow in a state in which an OFF signal is applied to the gate electrode 206. In a normally-off SIT, the OFF state is maintained by applying 0 V or negative voltage to the gate electrode 206. In the OFF state, a depletion region dr expands inside the drift region 202, and since the electric potential of the channel-doped layer is high, electrons (arrow e) can no longer travel from the source region 203 through the drift region 202, as shown in FIG. 10A. FIG. 10B shows the state in which a higher voltage than the voltage in the OFF state is applied to the gate electrode 206. When a voltage that is higher than the voltage in the OFF state is applied as the gate voltage, the depletion region dr is reduced, the electric potential of the channel-doped layer decreases, and the transistor is set in the ON state, and electron current (arrow e) flows from the source electrode 205 to the drain electrode 200. When a positive voltage is applied to the gate electrode 206, a pn junction formed between the gate and the source takes on a forward bias, and positive holes are injected (arrow h) from the gate region 204 to the drift region 202, as shown in FIG. 10C. Electrons are injected from the source region 203 due to the positive hole injection, and the electrical conductivity of the drift region increases so that the positive electric charge created by the injection of positive holes in the n-type drift region is neutralized. The ON resistance is thereby further reduced.
Thus, it is effective to apply the positive voltage to the gate electrode and increase the electrons injected from the source region into the drift region in order to obtain a lower ON voltage (resistance). In this case, the pn junction formed between the gate and source is given a forward bias, and the positive-hole electric current flows from the gate electrode to the source electrode. In order to operate the SIT at high efficiency, the device is preferably controlled with less gate electric current and with more drain electric current. For this reason, the electric current amplification factor (=drain electric current/gate electric current) is an important parameter.
Considered next is the effect of the recombination states brought about by damage that occurs due to high energy ion implantation. Since the diffusion coefficient of impurities in SiC is low, thermal diffusion that is commonly used in the case of silicon cannot be used when a selectively deep electroconductive region is formed in the SiC, and high energy (MeV) ion implantation is generally used. The gate region of a vertical junction transistor is also generally formed by high energy ion implantation. Crystal defects that cannot be restored by a following activation heat treatment remain in the ion implantation layer formed in this fashion and in the surrounding area. These crystal defects form the recombination states of electrons and positive holes. For this reason, when a forward bias is applied to the gate electrode 206 to cause an SIT such as that shown in FIG. 10C to operate, the positive holes (arrow h2) injected from the gate region 204 and electrons (arrow e2) injected from the source region 203 recombine via the recombination states (indicated by the symbol “x” in the drawing) that are present in the vicinity of the gate region 204, and the electric current amplification factor is reduced.
Described next is the normally-off characteristic. When some abnormality occurs-and the control signal to the gate electrode is cut off in a power device, the device is preferably set in an OFF state. For this reason, it is an important condition that power devices have a normally-off characteristic. In order for the structure of FIG. 8 described above to have a normally-off characteristic, the distance between adjacent gates and the width of the source must be made very narrow. FIGS. 11A and 11B are diagrams showing a comparison of a conventional device with narrow source and a device with a wide source. FIG. 11A shows the case in which the source is narrow and FIG. 11B shows the case in which the source is wide. Reference numeral 200 is a drain electrode, 201 is a drain region, 202 is a drift region, 203 is a source region, 204 is a gate region, 205 is a source electrode, and 206 is a gate electrode.
When the source is made narrow and the distance between the gates is reduced as in the device shown in FIG. 11A, manufacturing becomes difficult; the effective region (shown by the reference symbol ER in the diagram) of the entire device surface area is reduced, as shown in the diagram; and the ON voltage (resistance) increases as a result.
In the case of the SIT shown in FIG. 8, since the gate region is formed by high energy (MeV) injection, a considerable amount of recombination occurs via the recombination states created by ion implantation when the minority carrier is injected from the gate electrode, and the characteristics do not improve in bipolar mode operation that modulates conductivity in the high-resistance layer between the drain and the source. Also, since channel doping is not adopted in the structure, it is very difficult to obtain a normally-off characteristic.
In order to obtain a normally-off characteristic in the case of the JFET shown in FIG. 9, a very small trench structure with a width of 1.5 μm and a depth of about 2 μm must be made, and a gate layer must also be provided to the side walls of the trench, resulting in difficult manufacture. Also, the percentage of the source region that occupies the device must be made smaller, which hinders improvement of the ON voltage (resistance).
There is a drawback in that when a forward bias is applied to the gate electrode to operate a conventional junction transistor, the positive holes injected from the gate region and the electrons injected from the source region recombine via the surface states created by ion implantation, and the electric current amplification factor is reduced.
In order to obtain a normally-off characteristic in a convention junction transistor, the distance between adjacent gates and the width of the source must be made very narrow. When the width of the source is narrowed and the distance between gates is reduced, there is a drawback in that manufacturing becomes difficult, the effective region of the entire device surface area is reduced, and the ON voltage (resistance) increases as a result.
There is therefore a need to establish a method for manufacturing a junction semiconductor device whose structure makes it possible to establish simple steps for manufacturing a high-performance junction device having a normally-off characteristic that is required in the motor control of automobiles and other applications.